---++ Single-Channel Conversion of DFMux Firmware
The purpose of removing channels from the firmware is (was) to strip the existing RTL (100-tap FIRs and all) down to a version suitable for end-to-end simulation in System Generator. I've stopped working on this -- here's why.
Simulation is Just Too Slow. It's necessary to synthesize input signals at 25 MHz (minimum, assuming the 100 MHz clock has been ripped out) in order to provide input data to the
FPGA. Transferring these signals over ethernet or JTAG is the bottleneck; even when the output is decimated (by a minimum factor of 2048) the transfer rate is severely limiting. To get a reasonable number of samples out of the CIC, ignoring for a moment the FIR chain, takes a few minutes' cosimulation. Adding the FIR chain introduces a prohibitively long delay while the initial samples traverse the FIR, and reduces the output sample rate by another factor of 32=2^5.
The idea behind this simulation task is to add a convenient simulation double-check between design and verification. Design consists of both control (design, communication and sequencing of VHDL entities) and signal flow (the DSP bits, e.g. FIR taps and truncation.) End-to-end verification consists of a signal generator and spectrum analyzer. This testing step is mandatory, so any intermediate testing is only valuable if it is convenient and fast enough. It appears that the cosimulation work via System Generator is not.
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Topic revision: r2 - 2007-06-27 - GraemeSmecher