---+ Issues with Rev 0 CryoElectronics board that need to be addressed for Rev 2

In our lab we've upgraded to Altium version Summer 09, and no longer have easy access to the older version we used for this board. Please upgrade all files to the this newer version of Altium.

Changes to Schematics that do NOT affect layout

• Presently component U10 (precision resistive voltage divider) on all 4 reference voltage channels is MAX5490GC01000+T.
  Change the part number to MAX5490GA01000+T. (the "C" becomes an "A").
• Presently capacitors A(1-4)C5, D(1-4)C59, O(1-16)C21, I(1-16)C45 are INCORRECTLY 100nF. (this causes oscillations as the op-amps cannot drive a pure capacitive load).
  Change capacitors A(1-4)C5, D(1-4)C59, O(1-16)C21, I(1-16)C45 to be "DNL" in the schematics.
• On the "heater voltage regulators" page, R123 is INCORRECTLY listed as 330 and R124 incorrectly listed as 200.
  Change R123 to be 200 and R124 to be 330 (both should remain 1%, 0603).

• There are four nets that have names that are opposite to their functionality. We'd like to rename these nets in the schematics, to avoid wasting time with confusion in the future.
  • Please rename "dSensor+" to "DriveSensor-" on the Drive Channel Circuit page, which means that the corresponding bus on the Base Board Layout page will change, as will the corresponding net names on the Sensors and Heaters Connectors page.
  • Please rename "dSensor-" to "DriveSensor+" on the Drive Channel Circuit page, which means that the corresponding bus on the Base Board Layout page will change, as will the corresponding net names on the Sensors and Heaters Connectors page.
  • Note: I asked Adam (a young new engineer that recently joined in my team) if doing this would rip up all the tracks in the layout, causing a big headache and the necessity of re-laying the traces. He tried it and says that Altium handles this gracefully. "With regards to changing net names in Altium. I renamed a net on the clock board schematic in Altium, updated the pcb (via the menus), the net on the pcb successfully got automatically renamed whilst the track remained intact. Changing it back was similarly just as easy."
• Rename net FPGA_Heater_dIn_DAC (old name) to be FPGA_Heater_CLK_DAC (new name) on pages "Base Board Layout", "Mini Module", "Optp-Isolation and Control for the Heater Channels", and "Heater_DAC_OptoIso". The net's connectivity from U25A J2_61 to U17 pin 10 should be unchanged.
  Rename FPGA_Heater_CLOCK_DAC (old name) to be FPGA_Heater_DataIn_DAC (new name) on pages Base Board Layout", "Mini Module", "Optp-Isolation and Control for the Heater Channels", and "Heater_DAC_OptoIso". The net's connectivity from U25A J2_63 to U17 pin 9 should be unchanged.
  (This renaming should result in NO CHANGE TO THE COPPER. This corrects an error wherein the DIN and CLOCK net are reversed on the left side of opto-isolator U16. Since we have already accounted for this error in firmware (swapping the two FPGA pins), this modification merely brings the schematics up-to-date with what's already implemented in firmware.)
• Previously the resistors R21, R23, R25, R27, R29, R31, R33, R35, R37, R40, R43, R45, R47, R49, R51, R53, R73, R75, R77, R79, R82, R84, R87, R89, R91, R93, R95, R97 (these are pull up resistors in open collectors of opto-isolators) were INCORRECTLY set at 4.02K ohms.
  Change the resistor value to 500 ohms for all of these resistors.
• in text adjacent to J1 on "Drive Channel Circuit", change text from "*17.0k ---> Gain = 3.9" to new text "16.9k ---> Gain = 3.9"

Changes to Schematics that will affect layout

• Presently capacitors C114 C118 are INCORRECTLY connected between Regulator Pin3 and AGND.
  Change the connection on C114 and C118 to be between Regulator pin3 (BYP) and pin1 (OUT).
  Also, CHANGE the value of C114 and C118 to be 10n instead of 0.1uF.
• Presently pin 3 of U3 THS4131 on all 16 sensor drive channels is INCORRECTLY not connected to anything. This in an error that is only visible if you zoom in on the schematic, see DigitalFMux.IssueExplanationByTim
  Change the connection on U3 pin3 for all 16 sense channels to A+4.5v .
• Presently the pin2 of U31 (ILIM2 of voltage regulator) is not connected. We wish to increase the current limit of this regulator by 200mA as follows.
  Change the connection on U31 by connecting pin2 (ILIM2) to in1 (IN).

• Presently the 3.3V SYSCLK_25MHZ (25 MHz clock directly from oscillator) is connected to the mini module U25 via J2pin45 (which is pad C11 on the FPGA, that is on bank 3, configured to 2.5v and shares signals with the DDR SDRAM and configuration memories). This causes reverse current (shown in xapp453), which is bad.
  We wish to correct this as follows (see hand-sketch below):
  
  • separate net FPGA_CLK_INP from J2pin45 with a DNL 0603 resistor.
    
  • connect FPGA_CLK_INP to J2pin43 with a 0 ohm 0603 resistor.
    
• Presently components U20 and U21 are powered from H_3V3. We wish to add a new regulator to produce H_5V, and use it to power these components.
  (see attached PDF sketch NewHeaterDigitalOut.pdf)
  • Bring H+30-36v onto the sheet.
  • Add a new LT1962EM8 regulator (circuit similar to that of U30, though note that there were errors in the U30 circuit that are corrected above), with pin8 VIN H+30-36v, pin1 VOUT H_5V. There is room for this regulator on the board bottom, right under U20, U21.
    Note that the 10uF, 50V 1210 cap shown in the regulator circuit is too tall for the board bottom.
  • Change pin16 on U20 and U21 to connect to H_5V (formerly it was connected to H_3V3).
  • Change the part number for U20 and U21 to SN74AHC594PW (formerly it was 74LVX594TTR). The footprint is identical and does NOT need to be changed.
  • In addition, we wish to only use 4 of the outputs from U21 as follows:
    • Change pin1, pin3, pin5, pin7 of U21 to be NO CONNECT.
    • Connect nets heaterAUX2, heaterAUX4, heaterAUX6, and heaterAUX8 to PGND.

• Presently the board does NOT include a microSD flash card. We wish to add one.
  • We wish to use p/n multicomp TFCMF-20801B0T0 (newark 74M4846).
    The footprint is shown on page 1 of http://www.farnell.com/datasheets/20166.pdf (we have a tested footprint for this component from another board and will provide)
  • the microSD slot should be on the top-side of the board, between the J1 and J2 headers (such that it sits below the FPGA mini-module). The card should eject towards the board edge and the edge of the slot should line up with the board edge, such that it is possible to insert and remove the microSD card from the front of the board while it is in a rack.
  • The microSD slot should be connected as follows:
    

    pin	function	layout connection	which connects to FPGA pin
    1	DAT2	no connect	--
    2	Chip select/detect/DAT3	J2-56 through 50 ohm resistor	(FPGA pin C4)
    3	MOSI/CMD	J2-44	(FPGA pin W13)
    4	VDD	D_3V3	--
    5	SCK/CLK	J2-55	(FPGA pin D4)
    6	GND/VSS2	DGND	--
    7	MISO/DAT0	J2-43	(FPGA pin Y12)
    8	DAT1	no connect	--

    Please add this to the schematic on the mini-module page. It would be helpful to text-annotate the connections with the FPGA pin name.
    Also a 50 ohm resistor should be between pin 2 and J2-56.

• Presently the large, ceramic capacitors G(1-8)C27 and G(1-8)C54 on the bottom of the Cryo board p/n UMK325BJ106KM-T are too tall, and exceed the VME allowed dimensions on the board bottom.
  Tim, you may choose any one of these three options to address this issue:
  1. move these components to the top of the board (to make room, you can move other topside components to the bottom, so long as they are low profile).
     This is my preference, because it means we don't have to order new components.
  2. Replace each ONE of these 10u, 50V capacitors with TWO AVX 12105C475KAT2A capacitors 4.7u, 50V shown here http://canada.newark.com/avx/12105c475kat2a/ceramic-multilayer-capacitor/dp/96M1548 . These devices have the SAME footprint, but a much lower height.
     This is my second choice.
  3. Replace each ONE of these 10u, 50V capacitors with ONE 10u, 50V capacitor AVX 22205C106KAT2A with a 2220 footprint (much bigger) http://canada.newark.com/avx/22205c106kat2a/capacitor-10-uf-50v-2220-x7r/dp/15P4157
     Please avoid this option if possible, because these new capacitors have very long lead times.

Layout changes

• Presently the 2pin header J7 is INCORRECTLY too close to U33 oscillator (the pins of the header short to the metal on the oscillator).
  Move J7 further from U33 by translating it towards P1 by about 0.1" (or some other solution is probably ok too).
• Presently the 2pin header J8 is INCORRECTLY too close to U33 oscillator (the pins of the header short to the metal on the oscillator).
  Move J8 further from U33 by translating it towards B2L13 by about 0.05" (or some other solution is probably ok too).
• Presently the drive channels (Ox) are INCORRECTLY ordered 1,4,3,2,5,6,7,8,9,10,11,12,13,14,15,16 across the board (channels 4 and 2 are out of order).
  Interchange the board locations of drive channel 4 with drive channel 2 such that the ordering becomes 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 across the board.
  Note that all of the connections ARE correct, there are no changes needed to schematics.
  IMPORTANT Note that the SENSE (Ix) channels ARE correctly ordered from 1 to 16. (Historical note: we already tried fixing this problem once for Rev0 ... at that time the Sense channels were mis-ordered. I requested fixing the order of the Sense channels, but unfortunately in doing so, we messed up the ordering of the Drive channels... so please be careful with this one.)
• If there is space, please add plated mounting holes connected to AGND for 4-40 bolts (typical size is 0.113" for 4-40 clearance holes) everywhere on the board that they will fit.
  Looking very quickly at the gerbers for the board, there seems to be roughly 4 places (3 marked with arrows in the image below, and perhaps a fourth could go between J1 and J2 beneath the mini-module) where they might fit.
  An example of a good thru hole for this are the mounting holes for the HDDB44 connectors - you could use this padstack for these holes. If you can fit more than 4 holes, spread out at different locations, please do.
  

Foot prints that need updating or change

• (we have a tested footprint for this component from another board and will provide) U40 ADT7301ARTZ has completely wrong footprint. It is presently SOIC-6, but should instead be SPT-23. The correct footprint is found at http://www.analog.com/static/imported-files/Data_Sheets/ADT7301.pdf page15, figure 19.
• (we have a tested footprint for this component from another board and will provide) U22,U24,U35 SN74AVC2T45DCTR footprint is not a perfect fit to the component pads -- need to improve this component's footprint. The two rows of pads have too much separation (the distance from the center of pad1 to pad8 should be 3.1mm, it is presently about 4.7mm. The correct SSOP footprint is found at http://focus.ti.com/lit/ds/symlink/sn74avc2t45.pdf page 24 (note this DCT SSOP footprint is different from the DCU VSSOP footprint shown earlier in the document).
• The footprints for J4 and J11 (Phoenix 1725669 3pin connector) are missing guide-holes. Add three guide holes according to http://media.digikey.com/pdf/Data%20Sheets/Phoenix%20Contact%20PDFs/1725669.pdf page 4, top figure.
  The guide holes for J4, J11 should be such that the wire receptacles point towards the outside of the board.
• (we have a tested footprint for this component from another board and will provide)
  Presently RT1 (p/n YC248-JR0710KL, 10K pack of 8 resistors) has an INCORRECT footprint with 0.8mm pin pitch.
  Change this to the correct 0.5mm pitch footprint, shown at http://www.yageo.com/pdf/Pu-YC248_51_PbFree_L_1.pdf
  Presently RT2 and RT3 (p/n YC248-JR070RL, 0 ohm pack of 8 resistors) has an INCORRECT footprint with 0.8mm pin pitch.
  Change this to the correct 0.5mm pitch footprint, shown at http://www.yageo.com/pdf/Pu-YC248_51_PbFree_L_1.pdf
  

Assembly House Non-conformity Report

Tim, please read the Digico Non-conformity report from the assembly house, and double check that we've addressed all their layout-related issues (items 1 and 2 I'm unsure of - the others all seem to be addressed) for this new rev 2:

• 2009-04_DF01947-00_CryoelectronicsR0A_McGill.pdf:

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(Tim - ignore the stuff below this line)

Issues with PCB Fab

• One of the PCBs has a soldermask imperfection between the pads of O3U4. This board needs to be sent back to Coretec for inspection. It is board with S/N XX01, I think.
• The connection for the minimodule containing the FPGA and ethernet has skewed connectors making it difficult to plug the minimodule in to the cryoelectronics board.

Component issues:

• "MCG-02-0066 = EVP-AA402W, Switch, SM pushbutton SPST (instead of receiving EVPAA we received EVPAA202K)"
• "MCG-02-0087 = Zener Diode, SMBJ53, Zener Diodes SMD, 8.2V, 5W (instead of receiving 66B,39V,5WDO,214-AA we received MBJ5366B-TP Diode Zener 5W 39V SMB)"
• Item MCG-02-0046 L4,5,8 and 11 – location L8 (0805) doesn’t have the same pad format as the other 3 locations so L8 will not be installed. Matt - this connects analog ground to digital ground. Use 1206 0 ohm resistor instead.

Other issues that we will not fix with layout changes

• (nothing we can do about this except hope people aren't silly) the resistor RHS3 is a DNL resistor. If the user populates this resistor (to get heater power from 8V backplane), then stupidly connects a 35V power supply to the phoenix connector, he has the potential for shorting 35 volt supply to the 8V DfMux inputs, frying the DfMux boards. what do we want to do about this?
• (we choose not to address this) An oversight of the screw down cable securers (The green blocks) is that we will be unable to screw into them when the boards are in the rack
• Both the heater switches and DAC are powered by the heater power supply. If the digital power is cycled (or powered off), the old heater settings are kept and the FPGA has no way of reading them back. Thus, register reads will reflect the wrong values. (This is probably a design decision, but it means the heater power has to be cycled in order for the DACs and switches to power off.) This will be addressed in firmware, by writing zeros to all DACs and switches on power up.
• Graeme wrote: the existing mounting holes have unmasked vias (and a thick masked +35V via) pretty close to them. Standoffs might be dangerous here. I'm looking specifically at the corner by P2. (Matt doesn't understand this comment since the holes near P2 are for the euro96 connectors)
• The resistors R(21, 23, 25, 27, 29, 31, 33, 35, 38, 40, 43, 45, 47, 49, 51, 53, 73, 75, 77, 79, 82, 84, 87, 89, 91, 93, 95, 97 all pull up resistors in open collectors of opto-isolators) were set at 4.02K ohms and need to be changed to 200 ohms otherwise they make the time constant too long for the optoisolator LED's to keep up with the clocking.
  • : The DAC clock runs faster than the ADC clock (for which the value 200 Ω was selected.) This means we may have to revisit this choice again -- don't build a ton of boards without doublechecking this first!
  • : UPDATE: 200 Ω is fast enough, but makes the A_3V3 regulator U29 (bottom of board, near the analog voltage jumpers) very hot. The minimum recommended resistance (according to the optocoupler datasheet) is 330 Ω.
  • : UPDATE 2: We seem to have fixated on 500 Ω. Please use this value.
  • : UPDATE3: This may not be a good set of values to use for any optoisolators powered from the heater 3.3v supply. The efficiency of the 3.3v linear regulator (operating from 35v) is so abysmally low that current draw should be kept to a minimum. More to come.
  • : Update 4: The resistances R73, R75, R77, R79 are all fast signals on the order of 10 MHz. Please use the following resistances:
    • R73, R75, R77, R79: 500 ohms
    • R(21, 23, 25, 27, 29, 31, 33, 35, 38, 40, 43, 45, 47, 49, 51, 53, 82, 84, 87, 89, 91, 93, 95, 97): 4.02 k (the original value)
• Item MCG-02-0001 RT2 and RT3; the part size vs the pads are not the same so these will not be installed. need bigger Resistor x8. Matt the correct part is Digikey: 742C163000X (NOT IN STOCK!) Thus, it seems, we can use two EXB-38VR000V (0603x4).
• Item MCG-02-0011 RT1; the part size vs the pads are not the same so will not be installed. need bigger Resistor x8. Matt the correct part is Digikey: 742C163103JPTR (10k), ordered qty 100 reel april 17, 09
• Footprint of the MMM ought to be with guide holes and smaller pin holes (this comment doesn't make sense - ignoring for now

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This topic: CryoElectronics > CryoElectronicsDesignFiles > CryoElecRev0_Issues Topic revision: r36 - 2009-10-13 - GraemeSmecher

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