---+ Cryo board rev3b issues

(These have been pulled in and culled from the CryoElecRev3_Issues page.)

• Power routing issues
  • Oops! There's no VAuxP on the backplane, so the RHS1-RHS3 jumpers can only be used with the power header between backplane connections. Connect VAuxP to the backplane and doublecheck the other power nets. (First, doublecheck that this is actually what we want.)
• Memory issues:
  • Pull down DDR CKE pin if we want to use a preloading strategy
  • Move CKE from a 47-ohm terminating resistor to a 4.7k one (100 mW!)
  • Add terminating resistors for SDRAM DQS, DM pins
• Power sequencing and integrity issues:
  • The heater switches should be pulled LOW to avoid on-during-float behaviour These pins are pulled low by the LED
  • WDI pin on MAX6734 should have a pull-up pin (otherwise nothing drives it while the FPGA is being programmed, and we depend on it to wander predictably.) CHECK THIS
• Layout issues:
  • The serial number jumpers (J12-J19) shouldn't have traces on the top layer. It's too easy to cut the traces when snipping the jumpers. DNL these!
• Circuit Design Issues:
  • The ADC data outputs are ordinarily held high-Z and should be pulled up or down.
• Component loading issues:
  • Don't load R217 by default. The PHY clock is marginal (i.e. passes the V_hi threshold, but only just) with it. The comparator we use actually has fairly low current limits.

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This topic: CryoElectronics > DigitalFMux > CryoElectronicsDesignFiles > CryoElecRev3b_Issues Topic revision: r5 - 2011-08-05 - GraemeSmecher

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