---+ Example PCB Fabrication Notes

November 29, 2004   Contact   Matt Dobbs <MADobbs@lbl.gov> (514)398-6500

see .drd file for drill table.

Layer Stackup:

  1st upper-most layer:       TOP     routing  1 oz cu.
  2nd:                        INNER1  plane    1 oz cu.
  3rd:                        INNER4  routing  1 oz cu.
  4th:                        PWR     plane    1 oz cu.
  5th:                        INNER2  routing  1 oz cu.
  6th:                        INNER3  routing  1 oz cu.
  7th:                        GRND    plane    1 oz cu.
  8th lower-most layer:       BOTTOM  routing  1 oz cu.

The dielectric thickness shall be determined by the vendor such that
routing layers have (8mil) traces with controlled impedance between 75
and 100 ohms.


Fabrication NOTES: 

1.  Specifications 

  1.1 Fabricate in accordance with IPC600, latest revision.

  1.2 Producibility study- it is the responsibility of the supplier to
      conduct a thorough review of the artwork and media for
      manufactuability in the supplier's process compliance to all
      applicable specifications. LBNL must be advised in writing (in
      advance of manufacturing) of any changes, revisions, or
      corrections made or recommendations to ensure conformance to
      LBNL standards, and of any specifications that cannot be met.

  1.3 All notes are "unless otherwise specified".

2. Material

  2.1 NEMA Grade FR-4/Epoxy class, foil lamination structure for core
      and copper thickness; type GFN, in accordance with MIL-P-13949/4,11.

  2.2 Color to be opaque.

3. Soldermask
 
  3.1 Solder mask both sides with (green color) liquid photoimageable
      soldermask, 0.003" max thickness.

4. Drilling

  4.1 All hole diameters are finished sizes.
  4.2 All holes to be max +/-0.003" from true position.
  4.3 All hole diameters to be +/-0.003".
  4.4 An NC drill file has been supplied, see drill table.

5. Finish

  5.1 Plate holes thru with copper 0.001" min to 0.002" max thickness
      drill size dimension aply after plating.  

  5.2 Solder dip and hot air level with a 63/37% thin/lead coating,
      0.0002" min to 0.0010" max.

  5.3 Finished boards shall not have nicks, scratches, voids, exposed
      copper, poor plating or misdrilled holes.

  5.4 0.005" minimum trace width.

6. Silkscreen

  6.1 Silkscreen using white non-conductive epoxy or equivalent (both sides).
  6.2 No silkscreen allowed on exposed lands or in holes.
  6.3 Silkscreen must be a minimum of 3mm away from fiducial marks.
  6.4 Minimum clearance between silkscreen legend and untended vias, 
      pads or hiles to be 0.005".
  6.5 Registration to be +/-0.005" and must pass peel test.

7. Electrical test

  7.0 All boards shall be 100% electrically tested for opens/shorts to
      10 volts. MIL-SPEC boards to be tested at 40 volts.
  7.1 Apply test stamp in non-legend area on solder side of PCB.

8. Cleanliness
  8.1 Boards shall be free of fiber glass dust or any other foreign material.
  8.2 Finished boards must conform to 0.01 MG/IN max NAcL ionic 
      contamination as measured by the omega meter 600 SMD.
  8.3 Clean flux from boards, even if using "no-clean" flux.

9. Packaging- Each unit should be individually wrapped. Boards should
   be shipped in cardboard cartons with sufficient surrounding
   material to prevent shipping damage.

10. Bow and twist to be 0.007 IN/IN or 0.090 max according to IPC-A-600D.

11. Inspection: automatic optical inspection of all layers required.

12. Connector Finger plating: 15 micro inches minimum gold over 150
    micro inches minimum nickel.

-- MattDobbs - 14 Dec 2006

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